The present disclosure relates to semiconductor memory devices and, in particular, to three-dimensional semiconductor memory devices that have high reliability.
Higher integration of semiconductor devices is often required to satisfy consumer demands for superior performance and inexpensive prices. The integration density of two-dimensional (2D) or planar semiconductor devices is mainly determined by the area occupied by a unit memory cell. As such, in these devices, integration is heavily influenced by how finely patterns can be formed in the device. As extremely expensive process equipment is typically required to generate increasingly fine patterns, a practical limit exists with respect to increasing the integration density of two-dimensional semiconductor devices.
To overcome such a limitation, three-dimensional (3D) semiconductor memory devices that include three-dimensionally-arranged memory cells have been proposed. However, there are significant manufacturing obstacles in achieving low-cost, mass-production of 3D semiconductor memory devices, particularly in the mass-fabrication of 3D devices that maintain or exceed the operational reliability of their 2D counterparts.